个人信息

姓  名: 张源 性  別: 导师类型:
技术职称: 讲师 电子邮箱: yuanzhang@njupt.edu.cn
学术型硕士招生学科: 集成电路科学与工程、电路与系统
专业型硕士招生类别(领域): 集成电路工程、电子信息
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个人简介:

张源,博士毕业于湖南大学,长期从事集成电路设计、硬件安全、随机计算等领域研究,聚焦高吞吐量数字真随机数发生器、基于新型存储器的安全芯片等方面开展了大量研究工作,近5年以一作/通讯在IC设计顶会及权威期刊DACIEEE TCADACM TRETSACM TODAES发表高水平学术论文7篇,参与《网络安全技术物理不可克隆功能安全技术规范》国标编制,《集成电路硬件安全》教材编委,持有国家发明专利3。相关成果获选为CCF容错计算杰出成果(2025)。担任ITC-Asia 2026 Publicity ChairIEEE TCADTCAS-IIAsianHOST等期刊和会议审稿人。先后参与国家自然科学基金联合基金重点项目、173基础重点项目、国家重点研发计划等科研项目。

研究领域:

1.集成电路设计

2.硬件安全

3.物理不可克隆函数

4.真随机数发生器


招生信息:

欢迎对集成电路设计、集成电路硬件安全感兴趣的本科生、硕博研究生加入本课题组。本人为张吉良院长团队(集成电路硬件安全实验室)科研学术骨干,招收学生由我与张吉良院长联合指导。希望学生热爱科学研究、自驱力强、心态积极、乐于解决问题。


PS:本团队可再招收2026级硕士2人,欢迎有兴趣者附简历邮件联系

学术成果:

[1]Yuan Zhang, Kuncai Zhong, Jiliang Zhang, “DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency”, In Proceedings of the 61st ACM/IEEE Design Automation Conference (DAC), pp. 1-6, 2024.CCF A

[2]Yuan Zhang, Kuncai Zhong, and Jiliang Zhang, “High Throughput and Compact FPGA TRNGs Based on Hybrid Entropy, Reinforcement Strategies, and Automated Exploration”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 1, pp. 519-532, 2026. CCF A

[3]Yuan Zhang and Jiliang Zhang, “MCT-TRNG: Multi-Channel Tetrahedral TRNG via Metastability Enhanced Entropy with 2.2 Gbps Throughput”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 19, no. 7, pp. 1-21, 2026.CCF B

[4]Yuan Zhang and Jiliang Zhang, “A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing”, ACM Transactions on Design Automation of Electronic Systems(TODAES), vol. 29, no. 1, pp. 1-19, 2023.CCF B

[5]张源, 罗静茹, 张吉良, “SDL PUF:高可靠自适应偏差锁定PUF电路”, 电子与信息学报, vol. 46, no. 5, pp. 2274-2280, 2024.

[6]Yuan Zhang, Huaguo Liang, et al, “A High Reliability Physically Unclonable Function Based on Multiple Tunable Ring Oscillator”, Microelectronics Journal, vol. 117, pp. 105263, 2021.

[7]Zesheng Chen,Yuan Zhang*, Chaoqun Shen, “A Reconfigurable MRAM PUF with High Reliability”, Microelectronics Journal, vol. 163, pp. 106745, 2024.

[8]Jinwei Pu, Yan Xu, Yuan Zhang, Jiliang Zhang, “An Area-Efficient ML-DSA Accelerator With Interleaved and Dynamic Execution”, IEEE Transactions on Circuits and Systems I: Regular Papers, Early Access, 2026.

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